Communication systems typically utilize some form of clock system to synchronize communications between a transmitter and a receiver. In digital communication systems, the receiver typically operates at or near the same average frequency as the transmitting end to prevent loss of information. When digital signals are transported over a network of digital communication links, switching nodes, multiplexers, and transmission line interfaces, the task of keeping all the entities operating at the same average frequency is referred to as network synchronization.
Generally, in gigabit/second communication systems it is important that a receiver reads or samples the data waveform at an appropriate point in time relative to data waveform transitions. Many techniques can be utilized to determine when to sample the data waveform and this process is generally referred to as clock and data recovery (CDR). In a CDR system, when the timing of the receiver is synchronized with the data stream or data waveform, a sampling clock of the receiver will trigger a receiving component, such as a latch, a flip-flop or a register to acquire the logic value provided by the waveform at an appropriate time.
Applications for clock and data recovery abound in all facets of telecommunications, optical transceivers, data and storage networks, wireless products and computing systems in general. Traditional CDR systems utilize two or more system clocks or two sampling clock signals that cycle every bit interval or bit cycle. This “oversampling” approach is commonplace in typical CDR applications.
It can be appreciated that while the traditional oversampling topology in CDR systems is an effective way to recover data on a serial communication line, such a topology can be a costly and inefficient way to recover such data. Specifically, many CDR systems are typically required in a single integrated circuit system and each clock and associated clock distribution network required in such oversampling circuits typically consume a significant amount of power and further take up significant and valuable space on an integrated circuit. In such typical realizations of CDR systems, the first and second clocks together are typically utilized to sample the incoming waveform at different times, generally each signal initiating one sample per bit cycle. In this architecture, one of the two clocks typically sets when the data waveform is sampled for data acquisition while the other clock, along with the sampling clock, typically provides timing adjustment information to maintain synchronization between the incoming data stream and the CDR system.
CDR systems generally operate plesiochronously, where a transmitter clock operates at a “known” frequency and the receiver clock operates at a frequency within a small frequency offset of the transmitter clock's frequency. Plesiochronous operation occurs generally where critical timing moments occur nominally at the same rate and any variation in rate is constrained within specified limits. Although the frequency of the sampling clock can be set based on the frequency of the transmitter clock, unknown delays can occur between the transmitter and the receiver.
In addition, the timing of the received waveform can undergo random changes, known as timing jitter, which are induced by non-idealities of the clock circuitries and the transmission path. Furthermore, the presence of even small offsets between transmitter and receiver base frequencies will result in continuous changes in the relative phase between transmit and receive clock signals. Hence, the sample time(s) as determined by a data acquisition clock needs to be dynamically determined by the receiver in order to accurately recover data from the transmitted data waveform.
Ideally, clock and data recovery circuitry can perform voltage detection and set “phase slicing” levels in relation to a center of a pulse or a position between consecutive transitions of a differential signal. A differential signal has two signals that are one hundred eighty degrees out of phase and each signal can be carried on a separate conductor. These signals are often labeled as a data signal and a complementary data signal. Since the signals are 180 degrees out of phase, when data is being transmitted the signal on the data line will have the opposite value of the signal on the complementary data line.
It can be appreciated that signals cannot transition instantaneously and particularly in high speed gigabit/second communications signals, the time interval that the signal stays at its steady state may be shorter than the time required for the signal to transition, and thus, when certain bit patterns are present, the data waveform at the receiver can look more like a sine wave than a square wave. Accordingly, a picture of a differential signal often looks like two opposing sinusoidal waves that cross at an average voltage on the graph at various intervals, depending on the bit pattern being transmitted.
Recent advances in CDR systems have implemented additional circuits that can determine the center of the eye diagram, and/or utilize this data to determine a preferred time to sample the data stream. As stated above, virtually all of these designs have multiple system clocks and other control circuitry and such systems draw a significant amount of power and take up a lot of valuable space on an integrated circuit. Although these configurations do improve bit error rates, the penalty paid in power and size to realize the benefits provided by such circuits can be considerable.
As stated above, many CDR systems synchronize to the incoming data waveform by using two (or more) sampling clocks to detect the timing of waveform transitions on two differential data lines. One of these clocks also typically serves to sample the data waveform once per bit cycle, but not necessarily at a point in time a half-cycle removed from the times at which transition boundaries occur in the data waveform. Thus, data is acquired from the transmission line during a distinct time interval when the sampling clock is active. Clock generation and distribution circuits are among the biggest power consumers in an integrated circuit implementing a high data rate CDR. More particularly, clock circuits utilized in data receiving circuits are very “power hungry” because they typically have the highest operating frequency in a specific circuit.
The overall and relative phase precision of these multiple clocks must be accurate, demanding the use of complex, high power phase generation circuits. These circuits include delay-locked-loops (DLLs), phase-locked loops (PLLs), and phase rotator type clock generator circuits. Furthermore, the distribution of such high frequency clocks from, for example, a central clock generator to the receiver macro where the clocks are used, also demands significant power. Therefore, reducing the number of high frequency clocks that must be generated and for which precise phase relationships must be maintained is highly desirable.
Due to the significant shortcomings of traditional CDR systems as mentioned above, many low power CDR systems that have reduced clocks and clock networks have been proposed and investigated by many. CDR systems with reduced clock hardware can require significantly longer data acquisition times on power up and such systems can easily loose a data lock when noise, timing and other aberrations are present on the data line. Generally, such low power designs have a greatly reduced tracking capability for the initial timing and for changes in timing of the of the incoming data waveform. The unreliability, limited acquisition bandwidth and limited tracking bandwidth and general instability of such low power clock systems have kept such low power designs from becoming an acceptable solution to traditional CDR systems. Thus, it may be necessary provide an environment where the tracking capability of the CDR system can exceed the loop variations.
Currently, communication or information systems are transmitting and receiving data in the gigabit per second range. Increasing the accuracy of CDR amidst noise and distortions often present on a transmission line is a formidable task because the time intervals between signal transitions can become very small, demanding extreme precision of the data acquisition clock. As stated above, clock generation and distribution in CDR circuits is one of the biggest contributors to power consumption. Thus, a high precision, low power CDR architecture would be desirable.